1. Field of the Invention
This invention relates to semiconductor memory devices such as DRAMs (dynamic random access memories), particularly those having memory cells formed of one transistor and one capacitor, and a method of producing the same.
2. Description of the Related Art
The semiconductor memory device has been demanded to have a larger scale capacity and high speed operation capability as information equipment is developed. In order to respond to this demand, high integration, high speed response and high reliability are required for the semiconductor memory device. Particularly the memory cell array for storing information data must be absolutely integrated at a very high density. However, in the conventional semiconductor memory device, particularly in DRAM having memory cells formed of a transistor and a capacitor, the contact holes through which information lines are connected to the sources or the drains of the transistors must be separated by a certain distance or above from the gate electrodes of the transistors in order not to be made in contact therewith, and thus the memory cells should have design margins in size allowing for this separation.
FIGS. 4 and 5 show the structure of conventional stacked capacitor cells used in a one-transistor/one-capacitor type DRAM. In a method of producing this structure, the gate electrodes, or word lines 12 of MOS transistors 11 which constitute memory cells, are covered by an interfacial isolation film 13, and a photoresist (not shown) is coated over the entire surface of the substrate. Then, the photoresist is patterned by photolithography so that contact holes 15 can be later bored in the interfacial isolation film at the locations corresponding to the sources 14a of the MOS transistors 11.
Then, the interfacial isolation film 13 and the gate insulating film thereunder are selectively etched with this patterned resist used as a mask, so that the contact holes 15 are bored in those films. Thereafter, lower electrodes 17, insulating films 21 and upper electrodes 22 of capacitors 16 which constitute memory cells are deposited sequentially. In addition, the upper electrodes 22 are covered by an interfacial isolation film 23, and contact holes 24 reaching the drains 14b of the MOS transistors 11 are bored in the interfacial isolation film 23. Then, bit lines 25 are formed on the interfacial isolation film covering the holes.
FIGS. 4 and 5 show a pair of memory cells formed in one active region, which are formed by two MOS transistors 11 sharing one drain and serving as access transistors for the corresponding capacitors respectively.
In the conventional structure mentioned above, however, since the contact holes 15 are formed by photolithography, it is difficult to precisely bore the contact holes because of unsufficient precision of mask alignment in exposure. Therefore, a considerably large design margin 26 is necessary between the word line 12 and the contact hole 15 For example, under 1 .mu.m level design rules, the design margin 26 is required 0.5 through 1.0 .mu.m. This large design margin becomes a great interference with the memory cell area reduction for high-density DRAMs.